HDL Works HDL Design Entry EASE v7.3 R7 for Linux
HDLWorksHDLDesignEntryEASEv7.3R7forLinux英文正式版(混合語言等電路設計輸入最佳環境軟體
破解說明:
關掉主程式,破解檔放置於crack夾內,請將破解檔複製於主程式的安裝目錄內既可破解
內容說明:
EASE可提供對VHDL、Verilog、FPGA和ASIC的混合語言等電路設計輸入最佳環境，當完成設計後，
允許使用者自行選擇自己喜歡，由EASE提供獨立的合成與模擬工具。在市場上，EASE提供最直覺
的設計輸入環境，而且不管是對初學者或進階者，提供HDL設計所需的特性，可選擇文字方式或圖
形方式進行設計，EASE會自動依你選擇的編程語言將圖形轉換成對應的HDL語言。
VHDL(VHSICHardwaredescriptionlanguage-高速積體電路描述語言；VHSIC-VeryHighSpeed
IntegratedCircuit：高速積體電路)
英文說明:
EASEoffersthebestofbothworldswithyourchoiceofgraphicalor
textbasedHDLentry.Youdon?tneedtobeamasterofeitherVerilog
orVHDL.Whenyou'recreatinganewdesign,justenteryourdesignusing
yourmixofgraphicsandtext.EASEautomaticallygeneratesoptimized
HDLcodeforyouintheselectedlanguage-VHDLorVerilog.Industry
standardversioncontrolenvironmentsdealwithdesignandconfiguration
managementenablingmultipleuserstoworksimultaneouslyononeEASE
project.

Features&Benefits
-Graphicaldesignenvironmentwithautomatedgenerationofhierarchical
VHDLorVerilogcode
-Push-buttonimportoflegacyVerilogorVHDLdesignsandextractionof
graphicalhierarchy
-AdherestostateoftheartWindowslookandfeelforintuitiveoperation
-Standardscompliant(IEEE-1076-87&93VHDLandIEEE-1364Verilog)
-Truemulti-userdesignenvironmentandassociatedversioncontrol,
managedbyasophisticateddesignenvironmentbrowser
-Integratessmoothlywiththeindustry'smostpopularsimulatorsand
synthesistools
-Platformindependentdatabase
-IntegratedHDLlanguageeditor
-Hoterrorreporting
圖片說明:

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